SDR USRP N310: FPGA compilation error

[SanjayBi]

We are the seeing the Spurious signaling and would like to get help from NI support team for Transmisison filter provision from over the UHD driver. Our product at customer end is blocked due to FCC is not successfully done.

As per latest FCC testing, we are unable to utilize n5 and n77 band (3450-3550 MHz) for our B210 and N310 NIAB boxes since it is failing FCC Spurious testing (FCC testing results attached).

For B5, there are high spurious above -13 dBm coming at 3495 Mhz band.

For n77, since FCC limit is -40 dbm, Spurious emissions are above -40 dBm.

 We have tried to optimized all possible digital domain Txgain parameter to reduce the port power but unable to reduce the spurious emissions (Limit: n5 -> -13 dBm & n77 -> -40 dBm).

[santo_13]

So, you need to contact NI support  and unfortunately, NI discussion forum is not NI support, this is a public forum for users of NI's products to help each other.

[Velmenni]

Hi,

I am working on USRP N310 (Software Defined Radio). I have one module of USRP N310(S. No: 325F059).
I am facing some issues in FPGA compilation/Synthesis. The error message are as given below.

1. [Synth 8-10157] use of undefined macro 'RFNOC_EDGE_TBL_FILE' ["D:/FPGA/USRP_N310/uhd-master/uhd-master/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v":160]

2. [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

Note:Project Creation process

a. As per Ettus documents I download FPGA codes in Verilog from below link : https://github.com/EttusResearch/uhd
The downloaded file name is "uhd-master.zip"

b. The unzip downloaded "uhd-master.zip" file.
c. Create a project with the name of USRP_N310 in vivado & add folder/n3xx from uhd-master as shown below.
(D:\FPGA\USRP_N310\uhd-master\uhd-master\fpga\usrp3\top\n3xx) to FPGA project in xilinx Vivado 2022.2.
d. while synthesis the project in vivado then facing above errors shown in 1 & 2.

FPGA related Requirement:
1. Provide working projects.
2. FPGA design document (detailed description of design flow).
3. Can you provide FPGA code(RTL) in VHDL?

Project is very urgent so kindly provide support as soon as possible.